Semiconductor elements such as IC and the like are generally formed in a great number on a wafer, diced into individual chips and connected to various circuit boards for use. By further integration of IC at a large scale, the number of electrodes formed on the connection surface of one chip is increasing, and therefore, the size of each individual electrode becomes smaller and the arrangement of electrodes becomes congested.
To deal with the steep increase in the number of electrodes in recent years, electrodes are formed on the outer-periphery of the connection surface of a chip 100 in an alternate arrangement pattern following zigzag peaks, as shown in FIG. 6(a).
The “alternate arrangement pattern following zigzag peaks” means a pattern wherein, as shown in FIG. 6(b), individual electrodes E (E1, E2) are located on each vertex point J1, J2 of a zigzag line (sawtooth waveform line) J shown with a dashed line. This arrangement pattern depicts a checker pattern in two rows as a whole, as shown in FIG. 6(a).
In the following, this arrangement pattern is also referred to as a “zigzag arrangement pattern”.
The amplitude t2 (FIG. 6(a)) of the zigzag line in the zigzag arrangement pattern is determined in consideration of the size of electrodes, such that, as shown in FIG. 6(b), electrodes E1 located on one vertex point J1 do not contact electrodes E2 located on the other vertex point J2, even when transferred in the x-direction in the Figure.
The period (pitch) t1 of the zigzag line can be a short period, such that electrodes E1 located on one vertex point J1 come into contact with electrodes E2 located on the other vertex point J2 when they are transferred in the y-direction in the Figure, if the amplitude of the aforementioned zigzag line is determined with a sufficient room. The zigzag arrangement pattern is advantageous in that it permits setting of a short period.
The zigzag arrangement pattern of electrodes is used together with the stripe pattern of the wiring circuit board to be mentioned later, and enables fine pitch arrangement of electrodes and connection with the outside (e.g., JP-A-2003-249592).
On the other hand, as a technique for directly mounting a semiconductor element, a conductor part of a wiring circuit board is formed in a pattern corresponding to the positions of electrodes of a chip to afford mounting (bare chip mounting), directly connecting a chip with a wiring circuit board.
The wiring circuit board to be used for the bare chip mounting has a structure, as shown in FIG. 7 as a topically enlarged embodiment, wherein a band-like conductor pattern 101 is formed on an insulating substrate 100. In the wiring circuit board, a strip conductor 101 is formed in exposure to make a stripe pattern in an area corresponding to electrodes E and involved in electrical connection with the electrodes when a chip is set, thereby allowing connection of conductors with respective electrodes (dashed line) E. In this stripe pattern, individual strip conductors 101 extend in the direction (direction shown with an arrow y in the Figure) about perpendicular to the advancing direction of the zigzag arrangement pattern of electrodes E (direction shown with an arrow x in the Figure).
Each strip conductor 101 becomes an end at the position corresponding to respective electrodes E, whereby the end of a stripe pattern contains long ends 101L and short ends 101S alternately arranged therein (e.g., FIGS. 1, 2 of JP-A-2003-249592 and the like).
The edge of the end of each strip conductor often ends slightly extending from electrodes E to be connected, as shown in FIG. 7.
However, the present inventors investigated in detail the connection between an electrode formed in the above-mentioned zigzag arrangement pattern and a strip conductor formed in a stripe pattern, and found that, as shown in FIG. 8(a), positioning for mounting, and sizes of respective parts such as electrode width, conductor width and the like are required to have high precision, because electrodes E1 bridge to short-circuit two strip conductors 102 and 103 if the mounting position of a chip is deviated even a bit, making manufacture difficult.
In addition, it has been found that, when an anisotropic conductive adhesive comprising a conductive particle Q dispersed in a base material is used for connecting a chip with a wiring circuit board, as shown in FIG. 8(b), a conductive particle Q can be a short circuit path between an electrode E1 and a strip conductor 103, as shown by m in the Figure.
It is therefore an object of the present invention to provide a wiring circuit board having a structure capable of solving the above-mentioned problems, and to impart a wiring circuit board with a structure capable of suppressing a short circuit between an electrode and a wiring pattern even in the case of an electronic component having electrodes formed in high density and in a zigzag arrangement pattern.